The present invention relates to semiconductor chip performance measure and more specifically to a method and systems to determine the propagation delay in a semiconductor chip when the semiconductor chip is embedded in an electronic system, without requiring external measure devices or specific electrical contacts.
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or Application Specific Integrated Circuit (ASIC) device. These integrated circuits, also referred to as die or chip, may use many functions that previously could not be implemented on a single die. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site.
In addition, interconnecting the millions of transistors that may be present on a chip also poses difficulties. To aid in this task, new multiple layer metallization schemes have been developed that allow up to five or more distinct levels or layers of metal interconnect wires. In such multiple layer metallization schemes, the various metal interconnect wires typically have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness. These differences in the physical properties of the metal layers cause different metal layers to exhibit somewhat dissimilar electrical characteristics, resulting in disparities in propagation delays that a signal experiences when communicated over routing wires formed from the different metal layers. As a consequence, chip manufacturers perform measures so as to verify that propagation delays are comprised within predefined range values. Chips that don""t fulfill these requirements must be rejected.
However, such propagation delays may impact behavior of a whole electronic system, e.g. Printed Circuit Board (PCB) in several cases. For example, a chip may be out of designer specifications, even if this chip has been tested by chip manufacturer, when problems occur during test. Likewise, a chip designer may underestimate timing delays that may impact the whole electronic system functionality. Thus, measuring the propagation delay within a chip is helpful to determine the origin of detected problems as well as optimizing chip manufacturer processes or tests.
There is thus a need to evaluate propagation delay of chips mounted on PCBs. To that end, standard solutions consist in designing dedicated logic paths in the chips with corresponding dedicated pins. These pins may be accessed with signal generator and measure apparatus so as to measure the signal propagation delay along this logic path. When the propagation delay is evaluated for the known logic path, the propagation delay of each element of the logic path may be estimated and thus, the propagation delay of each element of the chip may also be estimated.
FIGS. 1 and 2 illustrate standard logic paths and corresponding timing analysis.
FIG. 1a shows a part of a chip 100 comprising pins 105 and 110 connected to a receiver 115 and a driver 120 respectively. A ring oscillator comprising logic elements 125-1 to 125-n is implemented on chip 100. First element 125-1 consists in a NAND gate. One input of NAND gate 125-1 is connected to receiver 115 and the other input is connected to the ring oscillator output. In this example, logic elements 125-2 to 125-n consist in inverters. The number of logic elements depends upon the propagation delay that must be evaluated and the system clock frequency. The ring oscillator output frequency must be very small compared with the system clock frequency. It is to be noticed that it is required to use an odd number of inverters in the ring oscillator logic path so that ring oscillator oscillates and does not reach a stable state. FIG. 1b illustrates a timing analysis of logic path comprised between pins 105 and 110 of chip 100. After a transition state of the input signal, from 0 to 1 in this example, an initialization phase occurs in the ring oscillator until its output frequency reaches a constant value, i.e. a constant frequency that depends upon the number and nature of ring oscillator logic elements and the propagation delay of each of these elements. Thus, the propagation delay may be easily determined. An approximation value D of the transmission delay is determined according to the following equation:                     D        =                  NC                      f            s_clk                                              (                  eq          .                      xe2x80x83                    ⁢          1                )            
where NC is the number of system clock pulses counted during one period of the ring oscillator output signal and fsxe2x80x94clk represents the frequency of the system clock, referred to as s_clk.
The approximation value D of the propagation delay may be improved by counting the number of system clock pulses during several periods, e.g. p, of the ring oscillator output signal. Thus, the improved approximation value D of the transmission delay is determined according to the following equation:                     D        =                  NC                      p            .                          f              s_clk                                                          (                  eq          .                      xe2x80x83                    ⁢          2                )            
FIG. 2a represents an alternative of the logic path described on FIG. 1, that does not comprised loop. Chip 100xe2x80x2 comprises pins 105xe2x80x2 and 110xe2x80x2 connected to a receiver 115xe2x80x2 and a driver 120xe2x80x2 respectively. A logic path consisting in logic elements 125xe2x80x2-1 to 125xe2x80x2-n, e.g. inverters, serially connected, links receiver 115xe2x80x2 to driver 120xe2x80x2. FIG. 2b shows an example of the behavior of input and output signals referred to as inputxe2x80x2 and outputxe2x80x2 respectively. When signal inputxe2x80x2 state changes, e.g. from 0 to 1, signal outputxe2x80x2 states changes after signal inputxe2x80x2 has been transmitted from pin 105xe2x80x2 to pin 110xe2x80x2, the state transition depends upon the logic path elements 125xe2x80x2-1 to 125xe2x80x2-n. For example, if n is an even number and signal inputxe2x80x2 state changes from 0 to 1, signal outputxe2x80x2 state will also change from 0 to 1. The time difference between transition of signals inputxe2x80x2 and outputxe2x80x2 corresponds to the propagation delay, as shown.
FIG. 3 illustrates the method that is generally used to measure propagation delay of a chip comprising a dedicated logic path and corresponding I/O pins such that the ones described above by reference to FIGS. 1 and 2. A PCB 300 comprises two semiconductor chips 305-1 and 305-2, e.g. switch devices using high-speed clock, controlled with a local processor 310. The board may also comprise other semiconductor chips, e.g. companion chips 315-1 to 315-4 and DC controller 320-1 and 320-2. PCB 300 includes at least one connector 325 that comprises pins 330-i or corresponding holes so that PCB may transmit/receive data to/from a back plane or another electronic system (not represented) as well as power and control signals. In order to measure the propagation delay of a chip, one needs to connect dedicated pins to measure apparatus (signal generator and analyzer), e.g. apparatus 335 and 340, using adapted probes. Depending upon PCB environment conditions, the probes may be attached to the chip dedicated pins, e.g. probes 345-1 and 345-2 are connected to pins 350-1 and 350-2 respectively, to specific conductive area of the PCB, e.g. probes 345xe2x80x2-1 and 345xe2x80x2-2 are connected to dedicated conductive areas 355-1 and 355-2 respectively, or to back plane or electronic system connectors (not represented). If the probes are connected to the chip dedicated pins through specific conductive area of the PCB or to back plane or electronic system connectors, the PCB designers must design corresponding tracks. These two last methods are generally not used in complex electronic system, e.g. network switch system, since signal tracks are surface consuming and may lead to signal interferences.
As a consequence, these propagation delay measurement methods present major drawbacks that mainly lie in the measure apparatus and the accesses to the chip or board that are required. When a system is in used in a customer location these requirements may be such that it is impossible to determine propagation delay. Thus, the system needs to be removed and sent back to the manufacturer for testing purposes. Furthermore, since these methods require dedicated pins on the chips, they are not adapted to chips that require more and more I/O, e.g. switch fabric.
Thus, it is a broad object of the invention to remedy the short-comings of the prior art as described here above.
It is another object of the invention to provide a method and systems to measure propagation delay within a chip without requiring measure apparatus.
It is still another object of the invention to provide a method and systems to measure propagation delay within a chip without requiring dedicated pins or specific electrical contacts.
It is a further object of the invention to provide a method and systems to measure propagation delay within a chip without removing the board embedding the chip from the electronic system in which it is plugged.
The accomplishment of these and other related objects is achieved by a method to measure the propagation delay of a chip, using a micro-processor, said chip comprising means for evaluating the propagation delay and memorization means, said method comprising the steps of:
transmitting a request from said microprocessor to said chip for evaluating propagation delay;
evaluating the propagation delay in said means for evaluating the propagation delay of said chip;
memorizing the evaluated propagation delay in said memorization means of said chip;
transmitting a request from said microprocessor to said chip for reading said evaluated propagation delay in said memorization means of said chip; and,
transmitting said evaluated propagation delay from said memorization means of said chip to said microprocessor,
and by a system to measure the propagation delay within a chip comprising:
a logic path;
counter means adapted to count pulses of a system clock according to the state of a signal generated in said logic path;
memorization means adapted to store the number of said pulses counted in said counter means; and,
a microprocessor interface,
wherein said number of said pulses counted in said counter means stored in said memorization means, characterizing said propagation delay, can be accessed with a microprocessor.
Further advantages of the present invention will become apparent to the ones skilled in the art upon examination of the drawings and detailed description. It is intended that any additional advantages be incorporated herein.